Synopsys announced complete IP solution for the PCI Express (PCIe) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys’ widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state.
Read full article on Help Net Security